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Arithmatica Licenses Verific HDL Component Software; Arithmatica's CellMath Tools Now Include Verilog Interface for Streamlined Verilog IC Implementation Flow
ALAMEDA, Calif.—(BUSINESS WIRE)—May 2, 2006—
Verific Design Automation today said that it has
licensed its hardware description language (HDL) Component Software to
Arithmatica Inc., the first company focused solely on using advances
in silicon math algorithms to lower costs and power and increase speed
for math-intensive integrated circuits (ICs).
Arithmatica has integrated Verific's Verilog parser and register
transfer level (RTL) elaborator with its CellMath tools to provide
tighter flow integration for Verilog users. The newly released
CellMath Verilog interface feature provides Verilog designers familiar
and easy-to-use syntax to specify robust datapath structures. The
Verilog input language utilizes pragmas to explicitly instantiate
advanced arithmetic datatypes such as carrysave wires and features
such as internal rounding.
Additionally, the companies have worked jointly on partitioning
datapath logic within a logic module for synthesis in CellMath
Designer, further streamlining the Verilog hardware designer's
implementation flow.
"Verific's best-in-class component software solutions allow us to
offer Verilog support to our customers, which we would not have been
able to do on our own," says Tony Curzon Price, Arithmatica's chief
executive officer. "Verific is a company dedicated to excellence in
customer support, top-quality HDL software and serves a formerly
underserved EDA component software market segment."
"Arithmatica has a unique product offering and a considerable
market opportunity," notes Michiel Ligthart, Verific's chief operating
officer. "We're delighted to work with Arithmatica and give its
customers Verilog input language support."
About Arithmatica
Arithmatica is the first company focused solely on using advances
in silicon math algorithms to lower costs and power and increase speed
for math-intensive ICs, such as those used in 3D graphics, imaging,
multimedia, wireline and wireless communications, and embedded
processing. Its unique technology, available through its tools
products and design services, provides differentiated improvement to
licensees' ICs. The company received its first venture funding in 2001
and is headquartered in Warwick, UK, with sales and support operations
in Palo Alto, Calif. For further information about how its silicon
math solutions increase silicon efficiency and boost productivity,
please visit: www.arithmatica.com.
About Verific Design Automation
Verific Design Automation was founded in 1999 by electronic design
automation (EDA) industry veteran Rob Dekker. It develops and sells
C++ source code-based SystemVerilog, Verilog and VHDL front ends --
parsers, analyzers and elaborators -- as well as a generic
hierarchical netlist database for EDA applications. Verific's
technology has been licensed in many applications, combined shipping
more than 45,000 end-user copies. Corporate headquarters is located
at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone:
(510) 522-1555. Facsimile number: (510) 522-1553. Email:
info@verific.com. Website: http://www.verific.com.
Verific Design Automation acknowledges trademarks or registered
trademarks of other organizations for their respective products and
services.
Contact:
Public Relations for Verific
Nanette Collins, 617-437-1822
Email Contact
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